Hardware accelerated visual attention algorithm

Polina Akselrod, Faye Zhao, Ifigeneia Derekli, Clément Farabet, Berin Martini, Yann LeCun, Eugenio Culurciello

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a hardware-accelerated implementation of a bottom-up visual attention algorithm. This algorithm generates a multi-scale saliency map from differences in image intensity, color, presence of edges and presence of motion. The visual attention algorithm is computed on a custom-designed FPGA-based dataflow computer for general-purpose state-of-the-art vision algorithms. The vision algorithm is accelerated by our hardware platform and reports x4 speedup when compared to a standard laptop with a 2.26 GHz Intel Dual Core processor and for image sizes of 480x480 pixels. We developed a real time demo application running at > 12 frames per second with the same size images. We also compared the results of the hardware implementation of the algorithm to the eye fixation points of different subjects on six video sequences. We find that our implementation achieves precisions of fixation predictions of up to 1/14th of the size of the video frames.

Original languageEnglish (US)
Title of host publication2011 45th Annual Conference on Information Sciences and Systems, CISS 2011
DOIs
StatePublished - 2011
Event2011 45th Annual Conference on Information Sciences and Systems, CISS 2011 - Baltimore, MD, United States
Duration: Mar 23 2011Mar 25 2011

Publication series

Name2011 45th Annual Conference on Information Sciences and Systems, CISS 2011

Other

Other2011 45th Annual Conference on Information Sciences and Systems, CISS 2011
CountryUnited States
CityBaltimore, MD
Period3/23/113/25/11

Keywords

  • FPGA
  • botttom-up
  • embedded hardware
  • hardware acceleration
  • saliency
  • vision systems
  • visual attention

ASJC Scopus subject areas

  • Information Systems

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