Hardware and Software Techniques for Heterogeneous Fault-Tolerance

With the advancements in the process technology, fault-tolerance against transient errors has emerged as an important design requirement for computing systems fabricated using nano-scale devices. Traditionally, redundancy-based techniques have been employed to detect and correct errors, and to achieve full system protection. However, as fault masking properties on different system levels have been observed and applications with lower accuracy demands or error-tolerant properties exist, reliability-heterogeneous architectures have recently paved the way for power-efficient dependable systems. In this paper, we will discuss the building blocks of such processors (both embedded and superscalar) with different fault-tolerant modes on the architecture level covering memory components like caches as well as in-order and out-of-order processor designs. We analyze the soft error vulnerability of different components and show how the variations in vulnerabilities can be exploited to improve the performance and power efficiency of such processors. We additionally show that a reliability-driven compiler can be leveraged to realize software-level heterogeneous fault tolerance by generating different reliable application versions with diverse reliability and performance properties.