Hardware-Supported Patching of Security Bugs in Hardware IP Blocks

Wei Kai Liu, Benjamin Tan, Jason M. Fung, Ramesh Karri, Krishnendu Chakrabarty

Research output: Contribution to journalArticlepeer-review


To satisfy various design requirements and application needs, designers integrate multiple Intellectual Property blocks (IPs) to produce a system-on-chip (SoC). For improved survivability, designers should be able to patch the SoC to mitigate potential security issues arising from hardware IPs; for increased flexibility, we propose adding programmable hardware-based support for monitoring and bug mitigation. However, it is a challenge to decide how much additional cost a designer should expend up front to deal with unknown, future issues. We propose an approach that guides designers towards maximizing the benefits of adding “patchability” to various IPs in the system, given a target resource overhead. We frame the design problem as an integer quadratic program and show that our approach achieves superior patchability compared to the naïve and baseline approaches for a given cost limit. Experimental results show that, when we set a cost limit of 2% FPGA ALM usage, our solution can generate a viable patching infrastructure with six patching blocks offering patches for seven different services in our case study.


  • Computer bugs
  • Costs
  • Hardware
  • Hardware Security.
  • IP networks
  • Monitoring
  • Patching
  • Security
  • Software
  • System-on-Chip

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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