Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems

Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz

Research output: Contribution to journalArticlepeer-review


As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target. Critically, unlike prior work, which focuses only on malicious packet modifications, a Trojan attack that exploits coherence can modify data in memory that was never touched and is not owned by the chiplet which contains the Trojan. Further, the Trojan need not even be physically between the victim and the memory controller to attack the victim's memory transactions. Here, we explore the fundamental attack vectors possible in chiplet-based systems and provide an example Trojan implementation capable of directly modifying victim data in memory. This work aims to highlight the need for developing mechanisms that can protect and secure the coherence scheme from these forms of attacks.

Original languageEnglish (US)
Pages (from-to)133-136
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - 2022


  • 2.5D integration
  • Hardware security
  • cache coherence
  • chiplets
  • hardware trojans
  • trusted computing

ASJC Scopus subject areas

  • Hardware and Architecture


Dive into the research topics of 'Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems'. Together they form a unique fingerprint.

Cite this