Hayat: Harnessing Dark Silicon and variability for aging deceleration and balancing

Elevated power densities result in the so-called Dark Silicon constraint that prohibits simultaneous activation of all the cores in an on-chIP system (in the full performance mode) to respect the safe thermal limits, thus enforcing a significant amount of on-chIP resources to stay 'dark' (i.e., power-gated). In this paper, we show that how Dark Silicon together with the manufacturing process induced variability can be harnessed to mitigate reliability threats in the nano-era. In particular, we propose a run-time system Hayat∗ that harnesses Dark Silicon to decelerate and/or balance temperature-dependent aging, while also considering variability in order to improve the overall system performance for a given lifetime. Experimental evaluation across a range of chIPs to account for process variations illustrates that our Hayat system can provide a significant aging/performance improvement and decelerates the chIP aging by 6 months - 5 years (depending upon the required lifetime constraint) compared to state-of-the-art techniques.