Heterogeneous BISR-approach using system level synthesis flexibility

Inki Hong, Miodrag Potkonjak, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

We propose a novel methodology for designing fault-tolerant real-time system to achieve optimal productivity on a single-chip multiprocessor platform using the heterogeneous built-in-self-repair(BISR) based graceful degradation and yield enhancement technique as an embedded optimization engine which exploits task-level scheduling and algorithm selection flexibility. We also developed a hardware fault model for modern superscalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals.

Original languageEnglish (US)
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PublisherIEEE
Pages289-294
Number of pages6
StatePublished - 1998
EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
Duration: Feb 10 1998Feb 13 1998

Other

OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
CityYokohama, Jpn
Period2/10/982/13/98

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Hong, I., Potkonjak, M., & Karri, R. (1998). Heterogeneous BISR-approach using system level synthesis flexibility. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 289-294). IEEE.