Abstract
We propose a novel methodology for designing fault-tolerant real-time system to achieve optimal productivity on a single-chip multiprocessor platform using the heterogeneous built-in-self-repair(BISR) based graceful degradation and yield enhancement technique as an embedded optimization engine which exploits task-level scheduling and algorithm selection flexibility. We also developed a hardware fault model for modern superscalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals.
Original language | English (US) |
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Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
Publisher | IEEE |
Pages | 289-294 |
Number of pages | 6 |
State | Published - 1998 |
Event | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn Duration: Feb 10 1998 → Feb 13 1998 |
Other
Other | Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) |
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City | Yokohama, Jpn |
Period | 2/10/98 → 2/13/98 |
ASJC Scopus subject areas
- General Engineering