Abstract
Using the flexibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous Built-In-Resiliency (HBIR). HBIR processor synthesis imposes several unique tasks on the synthesis process: (i) latency determination targeting k-unit fault-tolerance, (ii) application-to-faulty-unit matching and (iii) HBIR scheduling and assignment algorithms. We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of designs.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 406-411 |
| Number of pages | 6 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA Duration: Nov 10 1996 → Nov 14 1996 |
Other
| Other | Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design |
|---|---|
| City | San Jose, CA, USA |
| Period | 11/10/96 → 11/14/96 |
ASJC Scopus subject areas
- Software