TY - GEN
T1 - Hierarchical constraint conscious RT-level test generation
AU - Sinanoglu, O.
AU - Orailoglu, A.
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - The increasing complexity of ICs necessitates the use of test generation methodologies at higher levels of abstraction. We propose a computationally efficient RT-level test generation methodology that utilizes a divide and conquer approach. The hierarchical constraints for the module under test are identified through the proposed justification and propagation analysis. These constraints are then taken into account during the local test vector generation for the module under test, enabling the identification of the local test vectors that are guaranteed to be effective not only at the module-level but also at the system-level as well. High quality test sets are thus generated by the proposed methodology in a computationally efficient manner. Experimental results verify the performance boosts attained by the proposed methodology as well.
AB - The increasing complexity of ICs necessitates the use of test generation methodologies at higher levels of abstraction. We propose a computationally efficient RT-level test generation methodology that utilizes a divide and conquer approach. The hierarchical constraints for the module under test are identified through the proposed justification and propagation analysis. These constraints are then taken into account during the local test vector generation for the module under test, enabling the identification of the local test vectors that are guaranteed to be effective not only at the module-level but also at the system-level as well. High quality test sets are thus generated by the proposed methodology in a computationally efficient manner. Experimental results verify the performance boosts attained by the proposed methodology as well.
UR - http://www.scopus.com/inward/record.url?scp=84944317958&partnerID=8YFLogxK
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U2 - 10.1109/DSD.2003.1231961
DO - 10.1109/DSD.2003.1231961
M3 - Conference contribution
AN - SCOPUS:84944317958
T3 - Proceedings - Euromicro Symposium on Digital System Design, DSD 2003
SP - 312
EP - 318
BT - Proceedings - Euromicro Symposium on Digital System Design, DSD 2003
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Euromicro Symposium on Digital System Design, DSD 2003
Y2 - 1 September 2003 through 6 September 2003
ER -