Hierarchical constraint conscious RT-level test generation

O. Sinanoglu, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The increasing complexity of ICs necessitates the use of test generation methodologies at higher levels of abstraction. We propose a computationally efficient RT-level test generation methodology that utilizes a divide and conquer approach. The hierarchical constraints for the module under test are identified through the proposed justification and propagation analysis. These constraints are then taken into account during the local test vector generation for the module under test, enabling the identification of the local test vectors that are guaranteed to be effective not only at the module-level but also at the system-level as well. High quality test sets are thus generated by the proposed methodology in a computationally efficient manner. Experimental results verify the performance boosts attained by the proposed methodology as well.

Original languageEnglish (US)
Title of host publicationProceedings - Euromicro Symposium on Digital System Design, DSD 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages312-318
Number of pages7
ISBN (Electronic)0769520030, 9780769520032
DOIs
StatePublished - 2003
EventEuromicro Symposium on Digital System Design, DSD 2003 - Belek-Antalya, Turkey
Duration: Sep 1 2003Sep 6 2003

Publication series

NameProceedings - Euromicro Symposium on Digital System Design, DSD 2003

Other

OtherEuromicro Symposium on Digital System Design, DSD 2003
CountryTurkey
CityBelek-Antalya
Period9/1/039/6/03

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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