Hierarchical power budgeting for Dark Silicon chips

Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The emerging Dark Silicon limitation has led the application designers to carefully consider the available Thermal Design Power (TDP) budgets, hardware resources, and software characteristics. In this paper, we propose a hierarchical scheme for distributing the resources and TDP budget among concurrently executing applications with multi-threaded workloads under throughput constraints. Afterwards, the application-level TDP budget is partitioned among its threads depending upon their workloads, which can then be fine-tuned at run time considering workload variations. We evaluate our scheme for the next-generation, multi-threaded, High Efficiency Video Codec and demonstrate that up to 30.86% higher throughput is achieved compared to the state-of-the-art.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages213-218
Number of pages6
ISBN (Electronic)9781467380096
DOIs
StatePublished - Sep 21 2015
Event20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015 - Rome, Italy
Duration: Jul 22 2015Jul 24 2015

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2015-September
ISSN (Print)1533-4678

Other

Other20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015
CountryItaly
CityRome
Period7/22/157/24/15

Keywords

  • dark silicon
  • many-core system
  • parallel HEVC
  • power budgeting
  • resource allocation
  • Thermal design power

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Hierarchical power budgeting for Dark Silicon chips'. Together they form a unique fingerprint.

Cite this