It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility materials such as III-V, Ge, and graphene. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics is necessary. Atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through as well as reduction of native oxides by appropriate chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage, while preventing the re-growth of native oxides during the ex-situ sample transfer into the ALD reactor.