High-k dielectrics for Ge, III-V and graphene MOSFETs

S. Banerjee, E. Tutuc, S. Kim, T. Akyol, M. Jamil, D. Shahrjerdi, J. Donnelly, L. Colombo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility materials such as III-V, Ge, and graphene. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics is necessary. Atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through as well as reduction of native oxides by appropriate chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage, while preventing the re-growth of native oxides during the ex-situ sample transfer into the ALD reactor.

Original languageEnglish (US)
Title of host publicationECS Transactions - Physics and Technology of High-k Gate Dielectrics 7
Pages285-299
Number of pages15
Edition6
DOIs
StatePublished - 2009
Event7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society - Vienna, Austria
Duration: Oct 5 2009Oct 7 2009

Publication series

NameECS Transactions
Number6
Volume25
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other7th International Symposium on High Dielectric Constant Materials and Gate Stacks - 216th Meeting of the Electrochemical Society
CountryAustria
CityVienna
Period10/5/0910/7/09

ASJC Scopus subject areas

  • Engineering(all)

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