High-Level Approaches to Hardware Security: A Tutorial

Hammond Pearce, Ramesh Karri, Benjamin Tan

Research output: Contribution to journalArticlepeer-review


Designers use third-party intellectual property (IP) cores and outsource various steps in the integrated circuit (IC) design and manufacturing flow. As a result, security vulnerabilities have been rising. This is forcing IC designers and end users to re-evaluate their trust in ICs. If attackers get hold of an unprotected IC, they can reverse engineer the IC and pirate the IP. Similarly, if attackers get hold of a design, they can insert malicious circuits or take advantage of "backdoors"in a design. Unintended design bugs can also result in security weaknesses. This tutorial paper provides an introduction to the domain of hardware security through two pedagogical examples of hardware security problems. The first is a walk-through of the scan chain-based side channel attack. The second is a walk-through of logic locking of digital designs. The tutorial material is accompanied by open access digital resources that are linked in this article.

Original languageEnglish (US)
Article number45
JournalACM Transactions on Embedded Computing Systems
Issue number3
StatePublished - Apr 20 2023


  • Hardware
  • cybersecurity
  • logic locking
  • scan chain

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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