High-level power analysis for multi-core chips

Noel Eisley, Vassos Soteriou, Li Shiuan Peh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs)and embedded multi-processor systems-on-a-chip (MPSoCs), with on-chip networks increasingly becoming the defacto communication fabric between cores as the demand for on-chip bandwidth scales up. These multi-core chips are composed of two key subcomponents: processor cores and a network fabric. Rapid, early-stage power estimation of these multi-core chips is crucial in assisting compilers in determining the most efficient thread partitioning and place-ment. While prior work in high-level power analysis exists, the focus has been on uniprocessor cores and ignores the interactions between cores via the on-chip network, as well as the power contribution of the on-chip fabric itself. In this paper we propose a ?rst high-level power analysis framework that synergistically considers both computation and communication in a complete CMP system. Processor cores and the communication fabric are both abstracted as network nodes and links, so data dependencies, structural dependencies and communication dependencies are all modeled as resource contention, with resource utilization as a proxy for relative power. Our tool has been validated against the cycle-accurate BTL simulator of the MITRawCMP, showing an average speed up of 7X while achieving relative accuracy of 9.1%. We see this as a ?rst step towards enabling the implementation of parallelizing compilers that explore various power-performance tradeoffs for future multi-core chips.

Original languageEnglish (US)
Title of host publicationCASES 2006
Subtitle of host publicationInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems
Pages389-400
Number of pages12
DOIs
StatePublished - 2006
EventCASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems - Seoul, Korea, Republic of
Duration: Oct 22 2006Oct 25 2006

Publication series

NameCASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Other

OtherCASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems
CountryKorea, Republic of
CitySeoul
Period10/22/0610/25/06

Keywords

  • Chip multiprocessor (CMP)
  • Multi-core
  • Power analysis
  • Simulation
  • System-on-a-chip (SoC)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Fingerprint Dive into the research topics of 'High-level power analysis for multi-core chips'. Together they form a unique fingerprint.

  • Cite this

    Eisley, N., Soteriou, V., & Peh, L. S. (2006). High-level power analysis for multi-core chips. In CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems (pp. 389-400). (CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems). https://doi.org/10.1145/1176760.1176807