TY - GEN
T1 - High-Level Synthesis of Benevolent Trojans
AU - Pilato, Christian
AU - Basu, Kanad
AU - Shayan, Mohammed
AU - Regazzoni, Francesco
AU - Karri, Ramesh
N1 - Funding Information:
and viterbi. In motion, there are several bitwise operations. When eliminated, the multiplexers needed to drive the signals have a larger impact. mips and viterbi are small benchmarks and the additional resources contribute to a greater overhead, especially due to the additional controller. Merging the controllers has no impact on the datapath and also reduces the resources required to control the functional units. This optimization has more impact on small benchmarks. Figure 5(b) shows the overhead of FFs for the payload with separate and merged controllers. The overhead is small in all cases (∼3% even with separate controllers). In control-dominated designs (like gsm and mips), the FF overhead is larger (∼6-8%) since the datapath is small. In data-dominated designs (jpeg), controller FFs have a limited impact (∼1%). In case of separate controllers, we require few more FFs to encode the states in the payload controller. VII. CONCLUSIONS AND FUTURE WORK This paper offered a technique to implement IP watermarking using benevolent HTs. These HTs are blended into the IP component during HLS by reusing the resources, which reduced the hardware overhead. We suggested two alternative triggers based on either an external pin attached to the configuration registers and scan chains and on a predefined string of inputs. On average, the resource overhead for the offered technique is around 8% and 3% for LUTs and FFs. Benevolent HTs will be combined with other IP-protection countermeasures (e.g., chip obfuscation) to provide high robustness against state-of-the-art security properties. ACKNOWLEDGMENT This work is supported in part by National Science Foundation (NSF) (A#: 1526405). REFERENCES [1] F. Koushanfar, I. Hong, and M. Potkonjak, “Behavioral synthesis tech-niques for intellectual property protection,” ACM Trans. Des. Autom. Electron. Syst., vol. 10, no. 3, pp. 523–545, 2005. [2] Xilinx Inc., “Vivado design suite user guide - designing with IP (UG896),” 2017. [3] R. Nane et al., “A survey and evaluation of FPGA high-level synthesis tools,” IEEE Trans. CAD Integr. Circuits Syst., vol. 35, no. 10, pp. 1591– 1604, 2016. [4] M. Gupta, “Using 3rd party ip in asic/soc design,” 2017. [Online]. Available: https://www.design-reuse.com/articles/31313/using-3rd-party-ip-in-asic-soc-design.html [5] A. L. Oliveira, “Techniques for the creation of digital watermarks in sequential circuit designs,” IEEE Trans. CAD Integr. Circuits Syst., vol. 20, no. 9, pp. 1101–1117, 2001.
Publisher Copyright:
© 2019 EDAA.
PY - 2019/5/14
Y1 - 2019/5/14
N2 - High-Level Synthesis (HLS) allows designers to create a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). HLS reduces engineering effort and design-time errors, allowing the integration of additional features. This study introduces an approach to generate benevolent Hardware Trojans (HT) using HLS. Benevolent HTs are Intellectual Property (IP) watermarks that borrow concepts from well-known malicious HTs to ward off piracy and counterfeiting either during the design flow or in fielded integrated circuits. Benevolent HTs are difficult to detect and remove because they are intertwined with the functional units used to implement the IP. Experimental results testify to the suitability of the approach and the limited overhead.
AB - High-Level Synthesis (HLS) allows designers to create a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). HLS reduces engineering effort and design-time errors, allowing the integration of additional features. This study introduces an approach to generate benevolent Hardware Trojans (HT) using HLS. Benevolent HTs are Intellectual Property (IP) watermarks that borrow concepts from well-known malicious HTs to ward off piracy and counterfeiting either during the design flow or in fielded integrated circuits. Benevolent HTs are difficult to detect and remove because they are intertwined with the functional units used to implement the IP. Experimental results testify to the suitability of the approach and the limited overhead.
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U2 - 10.23919/DATE.2019.8715199
DO - 10.23919/DATE.2019.8715199
M3 - Conference contribution
AN - SCOPUS:85066604278
T3 - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
SP - 1124
EP - 1129
BT - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Y2 - 25 March 2019 through 29 March 2019
ER -