High-level synthesis of fault-secure microarchitectures

Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing import of quality metrics such as reliability and fault-tolerance are necessitating on-chip fault-tolerance. On-chip realization of a computation is fault-secure if no fault in the computation goes undetected. In this paper, we present high-level synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The proposed strategy selects intermediate computations for additional voting. The resulting class of fault secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations.