High-level synthesis of fault-secure microarchitectures

Ramesh Karri, Alex Orailogu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing import of quality metrics such as reliability and fault-tolerance are necessitating on-chip fault-tolerance. On-chip realization of a computation is fault-secure if no fault in the computation goes undetected. In this paper, we present high-level synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The proposed strategy selects intermediate computations for additional voting. The resulting class of fault secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Number of pages5
ISBN (Print)0897915771, 9780897915779
StatePublished - 1993
EventProceedings of the 30th ACM/IEEE Design Automation Conference - Dallas, TX, USA
Duration: Jun 14 1993Jun 18 1993

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123


OtherProceedings of the 30th ACM/IEEE Design Automation Conference
CityDallas, TX, USA

ASJC Scopus subject areas

  • General Engineering


Dive into the research topics of 'High-level synthesis of fault-secure microarchitectures'. Together they form a unique fingerprint.

Cite this