High-level synthesis of fault-tolerant ASICs

Advances in VLSI technology are making it feasible to integrate millions of transistors on a single chip. Such high levels of integration are leading to single-chip systems and on-chip fault-tolerance. Whereas methodologies for designing fault-tolerant systems have been well understood, software mechanisms for the automatic synthesis of fault-tolerant application specific ICs (ASICs) remain relatively unexplored. In this paper, we develop methodologies for the high-level synthesis of fault-tolerant ASICs that maximize performance in the presence of fault-tolerance and cost constraints. The faulttolerance constraints supported include number of faults per module (fault-masking constraint) and chip reliability (reliability constraint). Our experience with the system shows that (a) it is feasible to automate design for fault-tolerance, and (b) controlled interplay between cost, performance, and fault-tolerance, during high-level synthesis, helps synthesize high quality and costeffective fault-tolerant ASICs.