High-level synthesis of fault-tolerant ASICs

Ramesh Karri, Alex Orailoǧlu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Advances in VLSI technology are making it feasible to integrate millions of transistors on a single chip. Such high levels of integration are leading to single-chip systems and on-chip fault-tolerance. Whereas methodologies for designing fault-tolerant systems have been well understood, software mechanisms for the automatic synthesis of fault-tolerant application specific ICs (ASICs) remain relatively unexplored. In this paper, we develop methodologies for the high-level synthesis of fault-tolerant ASICs that maximize performance in the presence of fault-tolerance and cost constraints. The faulttolerance constraints supported include number of faults per module (fault-masking constraint) and chip reliability (reliability constraint). Our experience with the system shows that (a) it is feasible to automate design for fault-tolerance, and (b) controlled interplay between cost, performance, and fault-tolerance, during high-level synthesis, helps synthesize high quality and costeffective fault-tolerant ASICs.

Original languageEnglish (US)
Title of host publication1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780305930
StatePublished - 1992
Event1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States
Duration: May 10 1992May 13 1992

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310


Conference1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Country/TerritoryUnited States
CitySan Diego

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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