High mobility strained Ge MOSFETs with high-k gate dielectric on Si

Conventional scaling of bulk CMOS devices appears to have been stymied in recent years, leading to a flurry of activity in multi-gate and enhanced channel mobility MOSFETs With the advent of low leakage and low equivalent oxide thickness (EOT) high-k gate dielectrics, the limitation of Ge MOSFETs of not having a stable high-quality native gate oxide, has been mitigated and high mobility Ge channel MOSFETs have been demonstrated. Additionally, the lower band gap of Ge with the higher mobility should increase carrier injection from the source to the channel above that of Si. However, bulk Ge MOSFETs are limited by Ge substrates which are more expensive, fragile and have worse thermal conductivity than Si. Germanium channel MOSFETs fabricated on a Si substrate, incorporate the Ge channel either on a thick relaxed Si_1-xGe _x buffer layer or a strained Ge-on-insulator (SGOI) substrate, followed by a pure Ge epi layer. However such schemes are expensive and require complex processing. In this talk, we will discuss various schemes to circumvent some of these limitations. In one approach, Ge channels comparable to the inversion layer thickness were grown directly on Si substrates using a low temperature (∼370° C) ultra high vacuum-chemical vapor deposition (UHV-CVD). This technique requires neither an expensive starting substrate nor complex thick relaxed buffer layers. Thin (∼15nm) compressively-strained selective epitaxial grown (SEG) Ge film were achieved on small open Si active areas by ultra high vacuum-chemical vapor deposition (UHV-CVD). It was subsequently capped with a hafnium oxide gate dielectric at room temperature and then annealed. SEG growth and capping the Ge layers prior to thermal processing improve the stability of the layers, and the roughness of the epitaxial films. The compressively-strained Ge PMOSFETs show a ∼2X enhancements in drive current compared to Si devices. In other approaches, we have used thin, strained Ge buffer layers with rapidly varying Ge mole fractions to deflect threading dislocations away from the top Ge epitaxial layer. In yet another scheme, we have grown Ge:C partially strain compensated epitaxial films on Si in order to increase the allowable thermal budgets for MOSFET fabrication, and demonstrated enhanced hole mobilities in pMOSFETs compared to Si devices.