High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC

Cláudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fractional-pel interpolation for motion estimation and motion compensation is one of the key computational hotspots in the new High Efficient Video Coding (HEVC) standard. This work presents a high-throughput interpolation hardware architecture to improve performance of HEVC encoding and decoding. It employs two acceleration engines for luma and chroma filtering, each with 12-pel-parallel coarse-grained reconfigurable interpolation datapaths. An adaptive scheduling scheme manages the operation of these interpolation datapaths in different ways depending upon the prediction unit (PU) size and the execution scenario (i.e. motion estimation or motion compensation). We have implemented our hardware architecture in 150 nm technology. Compared to state-of-the-art techniques [12], our architecture required 49% less hardware area, while processing QFHD (3840×2160) resolution @ 30 fps.

Original languageEnglish (US)
Title of host publication2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings
Pages2091-2095
Number of pages5
DOIs
StatePublished - 2013
Event2013 20th IEEE International Conference on Image Processing, ICIP 2013 - Melbourne, VIC, Australia
Duration: Sep 15 2013Sep 18 2013

Publication series

Name2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings

Other

Other2013 20th IEEE International Conference on Image Processing, ICIP 2013
CountryAustralia
CityMelbourne, VIC
Period9/15/139/18/13

Keywords

  • Hardware Acceleration
  • HEVC
  • Interpolation Filter
  • Motion Compensation (MC)
  • Motion Estimation (ME)
  • Reconfigurable Datapaths

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition

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