High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC

Cláudio Machado Diniz; Muhammad Shafique; Sergio Bampi; Jörg Henkel

doi:10.1109/ICIP.2013.6738431

High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC

Cláudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Fractional-pel interpolation for motion estimation and motion compensation is one of the key computational hotspots in the new High Efficient Video Coding (HEVC) standard. This work presents a high-throughput interpolation hardware architecture to improve performance of HEVC encoding and decoding. It employs two acceleration engines for luma and chroma filtering, each with 12-pel-parallel coarse-grained reconfigurable interpolation datapaths. An adaptive scheduling scheme manages the operation of these interpolation datapaths in different ways depending upon the prediction unit (PU) size and the execution scenario (i.e. motion estimation or motion compensation). We have implemented our hardware architecture in 150 nm technology. Compared to state-of-the-art techniques [12], our architecture required 49% less hardware area, while processing QFHD (3840×2160) resolution @ 30 fps.

Original language	English (US)
Title of host publication	2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings
Publisher	IEEE Computer Society
Pages	2091-2095
Number of pages	5
ISBN (Print)	9781479923410
DOIs	https://doi.org/10.1109/ICIP.2013.6738431
State	Published - 2013
Event	2013 20th IEEE International Conference on Image Processing, ICIP 2013 - Melbourne, VIC, Australia Duration: Sep 15 2013 → Sep 18 2013

Publication series

Name	2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings

Other

Other	2013 20th IEEE International Conference on Image Processing, ICIP 2013
Country/Territory	Australia
City	Melbourne, VIC
Period	9/15/13 → 9/18/13

Keywords

Hardware Acceleration
HEVC
Interpolation Filter
Motion Compensation (MC)
Motion Estimation (ME)
Reconfigurable Datapaths

ASJC Scopus subject areas

Computer Vision and Pattern Recognition

Access to Document

10.1109/ICIP.2013.6738431

Cite this

Diniz, C. M., Shafique, M., Bampi, S., & Henkel, J. (2013). High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC. In 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings (pp. 2091-2095). Article 6738431 (2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings). IEEE Computer Society. https://doi.org/10.1109/ICIP.2013.6738431

High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC. / Diniz, Cláudio Machado; Shafique, Muhammad; Bampi, Sergio et al.
2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings. IEEE Computer Society, 2013. p. 2091-2095 6738431 (2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Diniz, CM, Shafique, M, Bampi, S & Henkel, J 2013, High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC. in 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings., 6738431, 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings, IEEE Computer Society, pp. 2091-2095, 2013 20th IEEE International Conference on Image Processing, ICIP 2013, Melbourne, VIC, Australia, 9/15/13. https://doi.org/10.1109/ICIP.2013.6738431

Diniz CM, Shafique M, Bampi S, Henkel J. High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC. In 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings. IEEE Computer Society. 2013. p. 2091-2095. 6738431. (2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings). doi: 10.1109/ICIP.2013.6738431

Diniz, Cláudio Machado ; Shafique, Muhammad ; Bampi, Sergio et al. / High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC. 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings. IEEE Computer Society, 2013. pp. 2091-2095 (2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings).

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High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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