Highly-scalable 3D CLOS NOC for many-core CMPs

Aamir Zia, Sachhidh Kannan, Garrett Rose, H. Jonathan Chao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Ab stract - In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.

Original languageEnglish (US)
Title of host publicationProceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010
Pages229-232
Number of pages4
DOIs
StatePublished - 2010
Event8th IEEE International NEWCAS Conference, NEWCAS 2010 - Montreal, QC, Canada
Duration: Jun 20 2010Jun 23 2010

Publication series

NameProceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010

Other

Other8th IEEE International NEWCAS Conference, NEWCAS 2010
CountryCanada
CityMontreal, QC
Period6/20/106/23/10

Keywords

  • 3D IC
  • CLOS
  • Network-on-chip
  • VLSI

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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