@inproceedings{31e12ccaf2374909b4fade57bce7dfc5,
title = "Highly-scalable 3D CLOS NOC for many-core CMPs",
abstract = "Ab stract - In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies.",
keywords = "3D IC, CLOS, Network-on-chip, VLSI",
author = "Aamir Zia and Sachhidh Kannan and Garrett Rose and Chao, {H. Jonathan}",
year = "2010",
doi = "10.1109/NEWCAS.2010.5603776",
language = "English (US)",
isbn = "9781424468058",
series = "Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010",
pages = "229--232",
booktitle = "Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010",
note = "8th IEEE International NEWCAS Conference, NEWCAS 2010 ; Conference date: 20-06-2010 Through 23-06-2010",
}