As technology scales below 45nm and circuit integration density increases, power distribution network (PDN) contributes significantly to the total chip yield, escape, and reliability. Due to lack of controllability and observability, the PDN failure analysis has become extremely challenging. A robust PDN is essential to ensure the performance of circuits on-chip, especially for low power, high-speed designs. The area of PDN and the number of power vias and lines have dramatically increased in complex designs over the past several years resulting in increased defects on PDNs. In this paper, we present an efficient pattern generation flow that targets open defects on PDN. In this flow, the circuit layout is divided into smaller regions based on PDN structures. A vector-pair is generated to increase the region switching activity so that the gates will experience a larger-than-threshold IR-drop which may cause a timing or logic failure if only an open defect exists on power vias or power lines in that region. Various open defects on power/ground lines and vias are inserted and their impacts on circuit performance are investigated. A region sorting procedure is included in the proposed flow to reduce the computing effort. The proposed pattern generation and verification flow is implemented on ITC'99 benchmark circuit b19 and experimental results on open defect-induced IR-drop is presented and analyzed in this paper.