Idle cycles based concurrent error detection of RC6 encryption

K. Wu, R. Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we will describe a Concurrent Error Detection (CED) technique that uses idle cycles in a data path to do the re-computation and demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability.

Original languageEnglish (US)
Title of host publicationIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Pages200-205
Number of pages6
StatePublished - 2001
EventIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001) - San Francisco, CA, United States
Duration: Oct 24 2001Oct 26 2001

Other

OtherIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001)
CountryUnited States
CitySan Francisco, CA
Period10/24/0110/26/01

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Wu, K., & Karri, R. (2001). Idle cycles based concurrent error detection of RC6 encryption. In IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (pp. 200-205)