Abstract
In this paper we will describe a Concurrent Error Detection (CED) technique that uses idle cycles in a data path to do the re-computation and demonstrate its benefits and drawbacks using RC6 encryption as a case study. The idle cycle based CED has low area overhead and performance penalty while maintaining strong CED capability.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems |
| Pages | 200-205 |
| Number of pages | 6 |
| State | Published - 2001 |
| Event | IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001) - San Francisco, CA, United States Duration: Oct 24 2001 → Oct 26 2001 |
Other
| Other | IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001) |
|---|---|
| Country/Territory | United States |
| City | San Francisco, CA |
| Period | 10/24/01 → 10/26/01 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering