Manufacturing process variations have become an important concern in the design of integrated circuits (IC) in the nanometer era. Process variations result in variability in the performance, power and thermal characteristics of ICs and, as a result, parametric yield loss. In this paper, we examine how process variation impact the 3D ICs compared to their planar (or 2D) counterparts. Using analytical models and empirical evaluation, we show that both from a clock frequency and thermal perspective, 3D ICs are worse impacted by process variations than their equivalent 2D implementations. While conventional variability mitigation techniques can be used to increase the resilience of 3D ICs to process variations, there are new opportunities for variability mitigation that are unique to 3D integration. In particular, in a die-to-die 3D bonding process, the decision of which die from one tier are bonded with which die from another can be made post fabrication after the bare die have been tested and assigned to frequency and leakage bins. In addition, for symmetric 3D design, it is additionally possible to decide the die stacking order for each 3D chip post manufacturing. We show that this flexibility in the bonding process can, in fact, result in significant performance and thermal yield improvement for 3D ICs.