The application and architecture of an experimental research prototype application specific integrated circuit designed to serve as a generic building block of the future broadband ISDN (B-ISDN) are described. The chip performs common asynchronous transfer mode (ATM) layer functions such as cell assembly and cell disassembly. A Media access control (MAC) protocol developed for a broadband customer premises network is also integrated in the chip. The chip operation modes are controlled through a microcontroller interface. The chip interfaces to the B-ISDN through a SONET STS-3c Framer chip. The ATM-layer chip has been designed using 1.2-μm CMOS technology with a die area of 5.4 mm × 5.4 mm and approximately 27,000 transistors.