TY - GEN
T1 - Innovation Practices Track
T2 - 40th IEEE VLSI Test Symposium, VTS 2022
AU - Qu, Gang
AU - Tan, Benjamin
AU - Pratihar, Kuheli
AU - Mukhopadhyay, Debdeep
AU - Karri, Ramesh
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - VLSI testing is essential to guarantee the correct functionality of the chip design. The recent advances in hardware security have posed new challenges for testing. In this IP session, we discuss the security in test and test for security through three talks. First, we give a brief overview of the security vulnerabilities and countermeasures in scan chain design, followed by a detailed discussion of a new configurable partial scan design approach. Second, we present the challenges in testing the security of design at various design stages and propose a strategy to identify potential security vulnerabilities in early design stages. Finally, we consider physical unclonable function (PUF) and develop an adaptive framework based on machine learning for the test and error correction of PUF designs.
AB - VLSI testing is essential to guarantee the correct functionality of the chip design. The recent advances in hardware security have posed new challenges for testing. In this IP session, we discuss the security in test and test for security through three talks. First, we give a brief overview of the security vulnerabilities and countermeasures in scan chain design, followed by a detailed discussion of a new configurable partial scan design approach. Second, we present the challenges in testing the security of design at various design stages and propose a strategy to identify potential security vulnerabilities in early design stages. Finally, we consider physical unclonable function (PUF) and develop an adaptive framework based on machine learning for the test and error correction of PUF designs.
KW - VLSI testing
KW - configurable scan
KW - error correcting code
KW - hardware security
KW - partial scan
KW - physical unclonable function
KW - scan chain
KW - security testing
KW - side channel analysis
UR - http://www.scopus.com/inward/record.url?scp=85132582738&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85132582738&partnerID=8YFLogxK
U2 - 10.1109/VTS52500.2021.9794269
DO - 10.1109/VTS52500.2021.9794269
M3 - Conference contribution
AN - SCOPUS:85132582738
T3 - Proceedings of the IEEE VLSI Test Symposium
BT - Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022
PB - IEEE Computer Society
Y2 - 25 April 2022 through 27 April 2022
ER -