Innovation Practices Track: Security in Test and Test for Security

Gang Qu, Benjamin Tan, Kuheli Pratihar, Debdeep Mukhopadhyay, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution


VLSI testing is essential to guarantee the correct functionality of the chip design. The recent advances in hardware security have posed new challenges for testing. In this IP session, we discuss the security in test and test for security through three talks. First, we give a brief overview of the security vulnerabilities and countermeasures in scan chain design, followed by a detailed discussion of a new configurable partial scan design approach. Second, we present the challenges in testing the security of design at various design stages and propose a strategy to identify potential security vulnerabilities in early design stages. Finally, we consider physical unclonable function (PUF) and develop an adaptive framework based on machine learning for the test and error correction of PUF designs.

Original languageEnglish (US)
Title of host publicationProceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022
PublisherIEEE Computer Society
ISBN (Electronic)9781665410601
StatePublished - 2022
Event40th IEEE VLSI Test Symposium, VTS 2022 - Virtual, Online, United States
Duration: Apr 25 2022Apr 27 2022

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference40th IEEE VLSI Test Symposium, VTS 2022
Country/TerritoryUnited States
CityVirtual, Online


  • VLSI testing
  • configurable scan
  • error correcting code
  • hardware security
  • partial scan
  • physical unclonable function
  • scan chain
  • security testing
  • side channel analysis

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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