Instruction-level impact comparison of RT- vs. gate-level faults in a modern microprocessor controller

Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We discuss the results of an extensive fault simulation study involving the control logic of a modern Alpha-like microprocessor. In this comparative study, faults are injected in both the RT- and the Gate-Level description of the design and are simulated under actual workload of the microprocessor, which is executing SPEC2000 benchmarks. The objective of this study is to analyze and contrast the impact of RT- and Gate-Level faults on the instruction execution flow of the microprocessor. The key observation is a pronounced consistency in the type and frequency of Instruction Level Errors (ILEs) arising due to RT- vs. Gate-Level faults. The motivation for this work stems from the need to understand the relative importance of low-level faults based on their instruction-level impact, in order to appropriately allocate error detection and/or correction resources. Hence, the consistency revealed through this study implies that such decisions can be made equally effective based on RT-Level fault simulation results, as with their far more computationally-expensive Gate-Level equivalents.

Original languageEnglish (US)
Title of host publicationProceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009
Number of pages6
StatePublished - 2009
Event2009 27th IEEE VLSI Test Symposium, VTS 2009 - Santa Cruz, CA, United States
Duration: May 3 2009May 7 2009

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other2009 27th IEEE VLSI Test Symposium, VTS 2009
Country/TerritoryUnited States
CitySanta Cruz, CA

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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