Intelligent on/off link management for on-chip networks

Andreas G. Savva; Theocharis Theocharides; Vassos Soteriou

doi:10.1109/ISVLSI.2011.13

Intelligent on/off link management for on-chip networks

Andreas G. Savva, Theocharis Theocharides, Vassos Soteriou

Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Links connecting on-chip components are a major source of power consumption in modern-day on-chip interconnects. Several efforts have henceforth focused on reducing the power consumption, the majority of which efforts target selected links for turning on and off. In this paper we propose an intelligent power management policy for networks-on-chip where links are turned off and switched back on based on a neural network, which processes link utilization as feedback from the system and determines which links are candidates for turning off and back on. The neural network is kept relatively small in terms of area and power consumption, as it is used to forecast the optimal utilization threshold for which underutilized links are turned off.

Original language	English (US)
Title of host publication	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages	343-344
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2011.13
State	Published - 2011
Event	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India Duration: Jul 4 2011 → Jul 6 2011

Publication series

Name	Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Other

Other	2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Country/Territory	India
City	Chennai
Period	7/4/11 → 7/6/11

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2011.13

Cite this

Intelligent on/off link management for on-chip networks. / Savva, Andreas G.; Theocharides, Theocharis; Soteriou, Vassos.
Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. 2011. p. 343-344 5992537 (Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Savva, AG, Theocharides, T & Soteriou, V 2011, Intelligent on/off link management for on-chip networks. in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011., 5992537, Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, pp. 343-344, 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, India, 7/4/11. https://doi.org/10.1109/ISVLSI.2011.13

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AB - Links connecting on-chip components are a major source of power consumption in modern-day on-chip interconnects. Several efforts have henceforth focused on reducing the power consumption, the majority of which efforts target selected links for turning on and off. In this paper we propose an intelligent power management policy for networks-on-chip where links are turned off and switched back on based on a neural network, which processes link utilization as feedback from the system and determines which links are candidates for turning off and back on. The neural network is kept relatively small in terms of area and power consumption, as it is used to forecast the optimal utilization threshold for which underutilized links are turned off.

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Intelligent on/off link management for on-chip networks

Abstract

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Other

ASJC Scopus subject areas

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