Intelligent on/off link management for on-chip networks

Andreas G. Savva, Theocharis Theocharides, Vassos Soteriou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Links connecting on-chip components are a major source of power consumption in modern-day on-chip interconnects. Several efforts have henceforth focused on reducing the power consumption, the majority of which efforts target selected links for turning on and off. In this paper we propose an intelligent power management policy for networks-on-chip where links are turned off and switched back on based on a neural network, which processes link utilization as feedback from the system and determines which links are candidates for turning off and back on. The neural network is kept relatively small in terms of area and power consumption, as it is used to forecast the optimal utilization threshold for which underutilized links are turned off.

Original languageEnglish (US)
Title of host publicationProceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Pages343-344
Number of pages2
DOIs
StatePublished - 2011
Event2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India
Duration: Jul 4 2011Jul 6 2011

Publication series

NameProceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Other

Other2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
CountryIndia
CityChennai
Period7/4/117/6/11

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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