Interconnect performance and energy-per-bit for post-CMOS logic circuits: Modeling, analysis, and comparison with CMOS logic

To overcome the energy dissipation limit facing virtually all field-effect devices including CMOS switches, there is a global search for devices using alternate state variables as the token of information. In this paper, physical models for latency and energy dissipation associated with various transport mechanisms are reviewed. Using stochastic wire length distribution models based on Rent's rule, the dependence of the average interconnect delay and energy dissipation on the number of gates in a circuit is obtained for alternative post-CMOS logic circuits. Further, it is demonstrated that the required number of repeaters increases rapidly with the circuit size if the token of information decays as it propagates (e.g. spin relaxation for electron spin). This puts an upper bound on the circuit size. For a spin relaxation length of L _s=2μm, the maximum circuit size for random logic is limited to 40 gates if less than 10% of the switches are to be used as interconnect repeaters and if the signal amplitude at the driver is twice the receiver's threshold. This maximum circuit size increases to 2000 gates if the spin relaxation length is increased to 8m at the same signal amplitude.