Investigating large integer arithmetic on Intel Xeon Phi SIMD extensions

In this paper, we investigate the Single Instruction Multiple Data (SIMD) extensions of the Intel Xeon Phi, and we analyze the benefits and limitations of its unique architecture in large integer arithmetic applications. The first generation Intel Xeon Phi, named Knights Corner, is a state-of-the-art many core coprocessor with up to 61 cores. Each Knights Corner core has 512-bit SIMD vectors, which are supported by a unique instruction set architecture, incompatible with existing SIMD schemes (SSE, AVX etc.). The second generation Intel Xeon Phi, Knights Landing, will include the standard 512-bit AVX512 SIMD extensions. We implement a multiplication scheme for large integers, which leverages the aforementioned SIMD extensions. Using this multiplication scheme, we discuss the SIMD extensions' performance for both Intel Xeon Phi generations. Preliminary results indicate that the Knights Corner SIMD speedup of large integer multiplication is limited by the absence of specific instructions that typically appear in common SIMD architectures. The emulation on Knights Landing (which includes backwards-compatible AVX512 extensions), on the contrary, shows that large integer multiplication can indeed benefit by the presence of 512-bit vectors, for commonly used 1024- and 2048-bit operands, compared to publicly available large arithmetic libraries.