TY - JOUR
T1 - ISMatch
T2 - A real-time hardware accelerator for inexact string matching of DNA sequences on FPGA
AU - Marchisio, Alberto
AU - Teodonio, Federico
AU - Rizzi, Antonello
AU - Shafique, Muhammad
N1 - Funding Information:
This work has been supported in part by the Doctoral College Resilient Embedded Systems, which is run jointly by the TU Wien's Faculty of Informatics and the UAS Technikum Wien. The authors acknowledge TU Wien Bibliothek for financial support through its Open Access Funding Programme.
Funding Information:
This work has been supported in part by the Doctoral College Resilient Embedded Systems , which is run jointly by the TU Wien’s Faculty of Informatics and the UAS Technikum Wien. The authors acknowledge TU Wien Bibliothek for financial support through its Open Access Funding Programme.
Publisher Copyright:
© 2023 The Author(s)
PY - 2023/3
Y1 - 2023/3
N2 - Since DNA strings suffer from variations like mutation, noisy sampling, and transmission, instead of searching for the exact match, the inexact string matching (ISM) of DNA sequences is preferred. Due to the large amount of data and massive data-dependency, the ISM algorithm is not suitable for being implemented into a general-purpose hardware. Towards this, we propose ISMatch, a novel specialized hardware architecture for computing the ISM in a fast and energy-efficient way. Our implementation on a Xilinx Ultrascale+ FPGA shows up to 70× and 2.2× clock cycles reduction compared to the ARM-based and the HLS implementations, respectively.
AB - Since DNA strings suffer from variations like mutation, noisy sampling, and transmission, instead of searching for the exact match, the inexact string matching (ISM) of DNA sequences is preferred. Due to the large amount of data and massive data-dependency, the ISM algorithm is not suitable for being implemented into a general-purpose hardware. Towards this, we propose ISMatch, a novel specialized hardware architecture for computing the ISM in a fast and energy-efficient way. Our implementation on a Xilinx Ultrascale+ FPGA shows up to 70× and 2.2× clock cycles reduction compared to the ARM-based and the HLS implementations, respectively.
KW - DNA sequence
KW - Energy efficiency
KW - FPGA
KW - Hardware accelerator
KW - Hardware design
KW - High Level Synthesis
KW - Inexact string matching
KW - Levenshtein distance
KW - Performance
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U2 - 10.1016/j.micpro.2023.104763
DO - 10.1016/j.micpro.2023.104763
M3 - Article
AN - SCOPUS:85146050413
SN - 0141-9331
VL - 97
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
M1 - 104763
ER -