TY - GEN
T1 - Leveraging CMOS design tools for QCA designs
AU - Kyosun, Kim
AU - Younbo, Oh
AU - Ramesh, Karri
AU - Alex, Orailoglu
PY - 2008
Y1 - 2008
N2 - This paper proposes a radical approach to designing nanoscale Quantum Dot Cellular Automata (QCA) designs by leveraging CMOS design tools such as those used for logic validation Based on design rules that guarantee deterministic digital behavior of QCA designs, we identified a finite set of legal arrangements for QCA cells. These cell arrangements can be composed to yield robust QCA building block gates (majority gate and inverters) and interconnect structures On one hand, such a hierarchical building blocks approach can be used to synthesize large scale, robust QCA designs. On the other hand, as shown in this paper, such a hierarchical building blocks approach can be used to check if QCA designs follow the robust design rules. If so, the implemented digital logic function can be extracted, translated into an equivalent Verilog or VHDL netlist, and validated using commercial CMOS design validation tools. Towards demonstrating the proposed approach, we designed a 2-bit QCA adder, extracted the digital logic, stored it in a common engineering database (OpenAccess) and validated the functionality using ModelSim CMOS simulator.
AB - This paper proposes a radical approach to designing nanoscale Quantum Dot Cellular Automata (QCA) designs by leveraging CMOS design tools such as those used for logic validation Based on design rules that guarantee deterministic digital behavior of QCA designs, we identified a finite set of legal arrangements for QCA cells. These cell arrangements can be composed to yield robust QCA building block gates (majority gate and inverters) and interconnect structures On one hand, such a hierarchical building blocks approach can be used to synthesize large scale, robust QCA designs. On the other hand, as shown in this paper, such a hierarchical building blocks approach can be used to check if QCA designs follow the robust design rules. If so, the implemented digital logic function can be extracted, translated into an equivalent Verilog or VHDL netlist, and validated using commercial CMOS design validation tools. Towards demonstrating the proposed approach, we designed a 2-bit QCA adder, extracted the digital logic, stored it in a common engineering database (OpenAccess) and validated the functionality using ModelSim CMOS simulator.
KW - Digital logic extraction
KW - Interoperability
KW - Quantum-dot cellular automata
KW - Signal integrity
UR - http://www.scopus.com/inward/record.url?scp=67650668041&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67650668041&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2008.4815714
DO - 10.1109/SOCDC.2008.4815714
M3 - Conference contribution
AN - SCOPUS:67650668041
SN - 9781424425990
SN - 9781424425990
T3 - 2008 International SoC Design Conference, ISOCC 2008
SP - II183-II186
BT - 2008 International SoC Design Conference, ISOCC 2008
T2 - 2008 International SoC Design Conference, ISOCC 2008
Y2 - 24 November 2008 through 25 November 2008
ER -