This paper proposes a radical approach to designing nanoscale Quantum Dot Cellular Automata (QCA) designs by leveraging CMOS design tools such as those used for logic validation Based on design rules that guarantee deterministic digital behavior of QCA designs, we identified a finite set of legal arrangements for QCA cells. These cell arrangements can be composed to yield robust QCA building block gates (majority gate and inverters) and interconnect structures On one hand, such a hierarchical building blocks approach can be used to synthesize large scale, robust QCA designs. On the other hand, as shown in this paper, such a hierarchical building blocks approach can be used to check if QCA designs follow the robust design rules. If so, the implemented digital logic function can be extracted, translated into an equivalent Verilog or VHDL netlist, and validated using commercial CMOS design validation tools. Towards demonstrating the proposed approach, we designed a 2-bit QCA adder, extracted the digital logic, stored it in a common engineering database (OpenAccess) and validated the functionality using ModelSim CMOS simulator.