TY - GEN
T1 - Leveraging variable function resilience for selective software reliability on unreliable hardware
AU - Rehman, Semeen
AU - Shafique, Muhammad
AU - Aceituno, Pau Vilimelis
AU - Kriebel, Florian
AU - Chen, Jian Jia
AU - Henkel, Jörg
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - State-of-the-art reliability optimizing schemes deploy spatial or temporal redundancy for the complete functionality. This introduces significant performance/area overhead which is often prohibitive within the stringent design constraints of embedded systems. This paper presents a novel scheme for selective software reliability optimization constraint under user-provided tolerable performance overhead constraint. To enable this scheme, statistical models for quantifying software resilience and error masking properties at function and instruction level are proposed. These models leverage a whole new range of reliability optimization. Given a tolerable performance overhead, our scheme selectively protects the reliability-wise most important instructions based on their masking probability, vulnerability, and redundancy overhead. Compared to state-of-the-art [7], our scheme provides a 4.84X improved reliability at 50% tolerable performance overhead constraint.
AB - State-of-the-art reliability optimizing schemes deploy spatial or temporal redundancy for the complete functionality. This introduces significant performance/area overhead which is often prohibitive within the stringent design constraints of embedded systems. This paper presents a novel scheme for selective software reliability optimization constraint under user-provided tolerable performance overhead constraint. To enable this scheme, statistical models for quantifying software resilience and error masking properties at function and instruction level are proposed. These models leverage a whole new range of reliability optimization. Given a tolerable performance overhead, our scheme selectively protects the reliability-wise most important instructions based on their masking probability, vulnerability, and redundancy overhead. Compared to state-of-the-art [7], our scheme provides a 4.84X improved reliability at 50% tolerable performance overhead constraint.
UR - http://www.scopus.com/inward/record.url?scp=84885621265&partnerID=8YFLogxK
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U2 - 10.7873/date.2013.354
DO - 10.7873/date.2013.354
M3 - Conference contribution
AN - SCOPUS:84885621265
SN - 9783981537000
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1759
EP - 1764
BT - Proceedings - Design, Automation and Test in Europe, DATE 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
Y2 - 18 March 2013 through 22 March 2013
ER -