Locating multiprocessor TLBs at memory

This paper compares the performance, in shared-memory multiprocessors, of locating translation-lookaside buffers (TLBs) at processors with that of locating TLBs at memory. Our comparison is based on trace-driven simulations of multiprocessors with log N-stage networks interconnecting N processors and N memory modules. For the systems and workloads studied, memory-based TLBs perform noticeably better than processor-based TLBs, provided that memory is organized as multiple paging arenas, i.e., multiple clusters of memory modules where the mapping of a page to a cluster is fixed. The cost of a processor-based TLB reload is at least log N because of network transit. In contrast, the cost of a memory-based TLB reload can be smaller, since network transits are not required. Furthermore, with multiple paging arenas, the number of reloads is smaller with memory-based TLBs.