Logic gate implementation for gray-scale morphology

Reitseng Lin; Edward K. Wong

doi:10.1016/0167-8655(92)90065-8

Logic gate implementation for gray-scale morphology

Reitseng Lin, Edward K. Wong

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, we show that the direct logic gate implementation of gray-scale morphology can be modified using threshold decomposition principle. The resulting new architecture has the advantage that the number of logic levels is not sensitive to structuring element size increases, yet it requires much less number of logic gates than a previously reported architecture having the same advantage.

Original language	English (US)
Pages (from-to)	481-487
Number of pages	7
Journal	Pattern Recognition Letters
Volume	13
Issue number	7
DOIs	https://doi.org/10.1016/0167-8655(92)90065-8
State	Published - Jul 1992

Keywords

Architecture
dilation
erosion
gray-scale morphology
image processing
stacking property
threshold decomposition

ASJC Scopus subject areas

Software
Signal Processing
Computer Vision and Pattern Recognition
Artificial Intelligence

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10.1016/0167-8655(92)90065-8

Cite this

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title = "Logic gate implementation for gray-scale morphology",

abstract = "In this paper, we show that the direct logic gate implementation of gray-scale morphology can be modified using threshold decomposition principle. The resulting new architecture has the advantage that the number of logic levels is not sensitive to structuring element size increases, yet it requires much less number of logic gates than a previously reported architecture having the same advantage.",

keywords = "Architecture, dilation, erosion, gray-scale morphology, image processing, stacking property, threshold decomposition",

author = "Reitseng Lin and Wong, {Edward K.}",

note = "Funding Information: This work was supported by the National Science Foundation under Grant Number IRI-8909188 and the New York State Center for Advanced Technology in Telecommunications.",

year = "1992",

month = jul,

doi = "10.1016/0167-8655(92)90065-8",

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journal = "Pattern Recognition Letters",

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T1 - Logic gate implementation for gray-scale morphology

AU - Lin, Reitseng

AU - Wong, Edward K.

N1 - Funding Information: This work was supported by the National Science Foundation under Grant Number IRI-8909188 and the New York State Center for Advanced Technology in Telecommunications.

PY - 1992/7

Y1 - 1992/7

N2 - In this paper, we show that the direct logic gate implementation of gray-scale morphology can be modified using threshold decomposition principle. The resulting new architecture has the advantage that the number of logic levels is not sensitive to structuring element size increases, yet it requires much less number of logic gates than a previously reported architecture having the same advantage.

AB - In this paper, we show that the direct logic gate implementation of gray-scale morphology can be modified using threshold decomposition principle. The resulting new architecture has the advantage that the number of logic levels is not sensitive to structuring element size increases, yet it requires much less number of logic gates than a previously reported architecture having the same advantage.

KW - Architecture

KW - dilation

KW - erosion

KW - gray-scale morphology

KW - image processing

KW - stacking property

KW - threshold decomposition

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U2 - 10.1016/0167-8655(92)90065-8

DO - 10.1016/0167-8655(92)90065-8

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VL - 13

SP - 481

EP - 487

JO - Pattern Recognition Letters

JF - Pattern Recognition Letters

IS - 7

ER -

Logic gate implementation for gray-scale morphology

Abstract

Keywords

ASJC Scopus subject areas

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