Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation

Logic locking has garnered significant attention due to its promising role in safeguarding intellectual property against potent threats across the integrated circuit supply chain. The locking mechanism introduces additional logic elements, so-called key-gates into a circuit, effectively securing the original design with a confidential key. This work utilizes locking to secure the hardware design of random-forest (RF) machine learning models. With the correct key, the design produces accurate inference outcomes; otherwise, it generates incorrect inferences. We explore field-programmable gate array (FPGA) implementation options to realize such locked inference accelerators. We propose an end-to-end methodology, spanning from the high-level RF hardware design, locking of those designs, to the FPGA implementation and performance evaluation. Our study employs Intel’s DE-10 standard FPGA, and we utilize multiple real-world datasets to illustrate the effectiveness of our approach.