Today’s integrated circuits are subject to a variety of attacks. Logic Locking is an area of hardware security that attempts to prevent reverse-engineering of integrated circuits based on a tamper-resistant memory. Despite significant attention from the research literature, no rigorous cryptographic modeling of logic locking and associated provable secure solutions have been proposed. Based on the observation that logic locking can be seen as a special case of hardware-based cryptographic program obfuscation, we propose rigorous definitions, borrowing approaches from modern cryptography (and, specifically, cryptographic program obfuscation), for both tamper-proof memories and logic locking of boolean circuits. We then prove two positive results: (1) the existence of a circuit computationally indistinguishable from a random oracle, assuming the existence of a pseudo-random function and of a tamper-proof memory, and (2) logic locking of general polynomial-size boolean circuits, assuming the existence of a pseudo-random generator and a tamper-proof memory. Our paper shows the possibility of provably boosting the capability of constructing a physical memory with a suitable tamper-resistant property into hardware-based obfuscation of any boolean circuit, as well as a practical hardware-based realization of a random oracle.