Low cost permanent fault detection using ultra-reduced instruction set co-processors

Sundaram Ananthanarayan, Siddharth Garg, Hiren D. Patel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a new, low hardware overhead solution for permanent fault detection at the microarchitecture/instruction level. The proposed technique is based on an ultra-reduced instruction set co-processor (URISC) that, in its simplest form, executes only one Turing complete instruction - the subleq instruction. Thus, any instruction on the main core can be redundantly executed on the URISC using a sequence of subleq instructions, and the results can be compared, also on the URISC, to detect faults. A number of novel software and hardware techniques are proposed to decrease the performance overhead of online fault detection while keeping the error detection latency bounded including: (i) URISC routines and hardware support to check both control and data flow instructions; (ii) checking only a subset of instructions in the code based on a novel check window criterion; and (iii) URISC instruction set extensions. Our experimental results, based on FPGA synthesis and RTL simulations, illustrate the benefits of the proposed techniques.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages933-938
Number of pages6
ISBN (Print)9783981537000
DOIs
StatePublished - 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Ananthanarayan, S., Garg, S., & Patel, H. D. (2013). Low cost permanent fault detection using ultra-reduced instruction set co-processors. In Proceedings - Design, Automation and Test in Europe, DATE 2013 (pp. 933-938). [6513642] (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/date.2013.196