Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector

Solomon Serunjogi, Kai Wei Lin, Mahmoud Rasras, Mihai Sanduleanu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a dual loop Clock and Data Recovery (CDR) circuit for high-end, low data rate, wireless transfer (100-200kb/s). Firstly, design tradeoffs for the single loop variant of the CDR are formulated which include jitter transfer (JT) function in frequency domain and long term jitter in time domain. These design rules are then used for the realization of a dual loop CDR consisting of tristate half rate frequency detector (FD), half rate linear phase detector (PD), bootstrapped current switch charge pump (CP) and ring based 4-phase VCO. All building blocks (except CP) are realized with plain vanilla CMOS digital circuits. In the proposed design, the output of the tri-state FD is zero when in lock and has no contribution to VCO jitter. In addition, the linear PD yields zero phase difference under the same lock condition. As a consequence, the CDR circuit can work with low jitter for low power applications.

Original languageEnglish (US)
Title of host publication25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
PublisherIEEE Computer Society
ISBN (Electronic)9781538628805
DOIs
StatePublished - Dec 13 2017
Event25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates
Duration: Oct 23 2017Oct 25 2017

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Other

Other25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
CountryUnited Arab Emirates
CityAbu Dhabi
Period10/23/1710/25/17

Keywords

  • CDR
  • Half-Rate
  • Jitter
  • Linear PD

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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