Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector

Solomon Serunjogi; Kai Wei Lin; Mahmoud Rasras; Mihai Sanduleanu

doi:10.1109/VLSI-SoC.2017.8203490

Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector

Solomon Serunjogi, Kai Wei Lin, Mahmoud Rasras, Mihai Sanduleanu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a dual loop Clock and Data Recovery (CDR) circuit for high-end, low data rate, wireless transfer (100-200kb/s). Firstly, design tradeoffs for the single loop variant of the CDR are formulated which include jitter transfer (JT) function in frequency domain and long term jitter in time domain. These design rules are then used for the realization of a dual loop CDR consisting of tristate half rate frequency detector (FD), half rate linear phase detector (PD), bootstrapped current switch charge pump (CP) and ring based 4-phase VCO. All building blocks (except CP) are realized with plain vanilla CMOS digital circuits. In the proposed design, the output of the tri-state FD is zero when in lock and has no contribution to VCO jitter. In addition, the linear PD yields zero phase difference under the same lock condition. As a consequence, the CDR circuit can work with low jitter for low power applications.

Original language	English (US)
Title of host publication	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538628805
DOIs	https://doi.org/10.1109/VLSI-SoC.2017.8203490
State	Published - Dec 13 2017
Event	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates Duration: Oct 23 2017 → Oct 25 2017

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Other

Other	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	10/23/17 → 10/25/17

Keywords

CDR
Half-Rate
Jitter
Linear PD

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2017.8203490

Cite this

Serunjogi, S., Lin, K. W., Rasras, M., & Sanduleanu, M. (2017). Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings Article 8203490 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203490

Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector. / Serunjogi, Solomon; Lin, Kai Wei; Rasras, Mahmoud et al.
25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. 8203490 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Serunjogi, S, Lin, KW, Rasras, M & Sanduleanu, M 2017, Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector. in 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings., 8203490, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, 10/23/17. https://doi.org/10.1109/VLSI-SoC.2017.8203490

Serunjogi S, Lin KW, Rasras M, Sanduleanu M. Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society. 2017. 8203490. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2017.8203490

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abstract = "This paper presents a dual loop Clock and Data Recovery (CDR) circuit for high-end, low data rate, wireless transfer (100-200kb/s). Firstly, design tradeoffs for the single loop variant of the CDR are formulated which include jitter transfer (JT) function in frequency domain and long term jitter in time domain. These design rules are then used for the realization of a dual loop CDR consisting of tristate half rate frequency detector (FD), half rate linear phase detector (PD), bootstrapped current switch charge pump (CP) and ring based 4-phase VCO. All building blocks (except CP) are realized with plain vanilla CMOS digital circuits. In the proposed design, the output of the tri-state FD is zero when in lock and has no contribution to VCO jitter. In addition, the linear PD yields zero phase difference under the same lock condition. As a consequence, the CDR circuit can work with low jitter for low power applications.",

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N2 - This paper presents a dual loop Clock and Data Recovery (CDR) circuit for high-end, low data rate, wireless transfer (100-200kb/s). Firstly, design tradeoffs for the single loop variant of the CDR are formulated which include jitter transfer (JT) function in frequency domain and long term jitter in time domain. These design rules are then used for the realization of a dual loop CDR consisting of tristate half rate frequency detector (FD), half rate linear phase detector (PD), bootstrapped current switch charge pump (CP) and ring based 4-phase VCO. All building blocks (except CP) are realized with plain vanilla CMOS digital circuits. In the proposed design, the output of the tri-state FD is zero when in lock and has no contribution to VCO jitter. In addition, the linear PD yields zero phase difference under the same lock condition. As a consequence, the CDR circuit can work with low jitter for low power applications.

AB - This paper presents a dual loop Clock and Data Recovery (CDR) circuit for high-end, low data rate, wireless transfer (100-200kb/s). Firstly, design tradeoffs for the single loop variant of the CDR are formulated which include jitter transfer (JT) function in frequency domain and long term jitter in time domain. These design rules are then used for the realization of a dual loop CDR consisting of tristate half rate frequency detector (FD), half rate linear phase detector (PD), bootstrapped current switch charge pump (CP) and ring based 4-phase VCO. All building blocks (except CP) are realized with plain vanilla CMOS digital circuits. In the proposed design, the output of the tri-state FD is zero when in lock and has no contribution to VCO jitter. In addition, the linear PD yields zero phase difference under the same lock condition. As a consequence, the CDR circuit can work with low jitter for low power applications.

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KW - Jitter

KW - Linear PD

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Low-jitter, plain vanilla CMOS CDR with half-rate linear PD and half rate frequency detector

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Keywords

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