Low power design of the next-generation High Efficiency Video Coding

Muhammad Shafique, Jorg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper provides a comprehensive analysis of the computational complexity, power consumption, temperature, and memory access behavior for the next-generation High Efficiency Video Coding (HEVC) standard. We highlight the associated design challenges and present several low-power algorithmic and architectural techniques for developing power-efficient HEVC-based multimedia system. We explore the interplay between the algorithms and architectures to provide high power efficiency while leveraging the application-specific knowledge and video content characteristics.

Original languageEnglish (US)
Title of host publication2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Pages274-281
Number of pages8
DOIs
StatePublished - 2014
Event2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
Duration: Jan 20 2014Jan 23 2014

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
CountrySingapore
CitySuntec
Period1/20/141/23/14

Keywords

  • algorithm
  • analysis
  • architecture
  • energy efficiency
  • hardware accelerator
  • HEVC
  • low power design
  • power management
  • video coding
  • video memory

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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