TY - JOUR
T1 - MacLeR
T2 - Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices
AU - Khalid, Faiq
AU - Hasan, Syed Rafay
AU - Zia, Sara
AU - Hasan, Osman
AU - Awwad, Falah
AU - Shafique, Muhammad
N1 - Funding Information:
Manuscript received April 18, 2020; revised June 12, 2020; accepted July 6, 2020. Date of publication October 2, 2020; date of current version October 27, 2020. This work was supported in part by the Austrian Research Promotion Agency (FFG) and the Austrian Federal Ministry for Transport, Innovation, and Technology (BMVIT) under the “ICT of the Future” Project, IoT4CPS: Trustworthy IoT for Cyber-Physical Systems. This article was presented in the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2020 and appears as part of the ESWEEK-TCAD special issue. (Corresponding author: Faiq Khalid.) Faiq Khalid is with the Institute of Computer Engineering, Technische Universität Wien, 1040 Vienna, Austria (e-mail: [email protected]).
Funding Information:
This work was supported in part by the Austrian Research Promotion Agency (FFG) and the Austrian Federal Ministry for Transport, Innovation, and Technology (BMVIT) under the ?ICT of the Future? Project, IoT4CPS: Trustworthy IoT for Cyber-Physical Systems
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2020/11
Y1 - 2020/11
N2 - Traditional learning-based approaches for runtime hardware Trojan (HT) detection require complex and expensive on-chip data acquisition frameworks, and thus incur high area and power overhead. To address these challenges, we propose to leverage the power correlation between the executing instructions of a microprocessor to establish a machine learning (ML)-based runtime HT detection framework, called MacLeR. To reduce the overhead of data acquisition, we propose a single power-port current acquisition block using current sensors in time-division multiplexing, which increases accuracy while incurring reduced area overhead. We have implemented a practical solution by analyzing multiple HT benchmarks inserted in the RTL of a system-on-chip (SoC) consisting of four LEON3 processors integrated with other IPs, such as vga_lcd, RSA, AES, Ethernet, and memory controllers. Our experimental results show that compared to state-of-the-art HT detection techniques, MacLeR achieves 10% better HT detection accuracy (i.e., 96.256%) while incurring a $7\times $ reduction in area and power overhead (i.e., 0.025% of the area of the SoC and < 0.07% of the power of the SoC). In addition, we also analyze the impact of process variation (PV) and aging on the extracted power profiles and the HT detection accuracy of MacLeR. Our analysis shows that variations in fine-grained power profiles due to the HTs are significantly higher compared to the variations in fine-grained power profiles caused by the PVs and aging effects. Moreover, our analysis demonstrates that on average, the HT detection accuracy drops in MacLeR is less than 1% and 9% when considering only PV and PV with worst case aging, respectively, which is $\approx 10\times $ less than in the case of the state-of-the-art ML-based HT detection technique.
AB - Traditional learning-based approaches for runtime hardware Trojan (HT) detection require complex and expensive on-chip data acquisition frameworks, and thus incur high area and power overhead. To address these challenges, we propose to leverage the power correlation between the executing instructions of a microprocessor to establish a machine learning (ML)-based runtime HT detection framework, called MacLeR. To reduce the overhead of data acquisition, we propose a single power-port current acquisition block using current sensors in time-division multiplexing, which increases accuracy while incurring reduced area overhead. We have implemented a practical solution by analyzing multiple HT benchmarks inserted in the RTL of a system-on-chip (SoC) consisting of four LEON3 processors integrated with other IPs, such as vga_lcd, RSA, AES, Ethernet, and memory controllers. Our experimental results show that compared to state-of-the-art HT detection techniques, MacLeR achieves 10% better HT detection accuracy (i.e., 96.256%) while incurring a $7\times $ reduction in area and power overhead (i.e., 0.025% of the area of the SoC and < 0.07% of the power of the SoC). In addition, we also analyze the impact of process variation (PV) and aging on the extracted power profiles and the HT detection accuracy of MacLeR. Our analysis shows that variations in fine-grained power profiles due to the HTs are significantly higher compared to the variations in fine-grained power profiles caused by the PVs and aging effects. Moreover, our analysis demonstrates that on average, the HT detection accuracy drops in MacLeR is less than 1% and 9% when considering only PV and PV with worst case aging, respectively, which is $\approx 10\times $ less than in the case of the state-of-the-art ML-based HT detection technique.
KW - Hardware security
KW - hardware trojans
KW - LEON3
KW - machine learning
KW - microprocessor
KW - power profiling
UR - http://www.scopus.com/inward/record.url?scp=85096033010&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85096033010&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2020.3012236
DO - 10.1109/TCAD.2020.3012236
M3 - Article
AN - SCOPUS:85096033010
SN - 0278-0070
VL - 39
SP - 3748
EP - 3761
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 11
M1 - 9211562
ER -