Mapping nested loop algorithms into multi-dimensional systolic arrays

Pei Zong Lee, Zvi M. Kedem

Research output: Contribution to journalConference articlepeer-review


This study is concerned with transforming depth p-nested for loop algorithms into q-D systolic VLSI arrays, where 1 ≤ q ≤ p - 1. Previously, there existed necessary and sufficient conditions only for the cases when q = p - 1 and q = 1. The authors fill in this gap by giving formal conditions for correct transformations of a p-nested loop algorithm into a q-D systolic array for any q, 1 ≤ q ≤ p - 1. The techniques developed contribute towards the automatic design of special-purpose systolic arrays and automatic compilation onto more general-purpose programmable arrays.

Original languageEnglish (US)
Pages (from-to)206-210
Number of pages5
JournalProceedings of the International Conference on Parallel Processing
StatePublished - 1989
EventProceedings of the 1989 International Conference on Parallel Processing - University Park, PA, USA
Duration: Aug 8 1989Aug 12 1989

ASJC Scopus subject areas

  • Hardware and Architecture

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