Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays

Pei Zong Lee, Zvi Meir Kedem

Research output: Contribution to journalArticlepeer-review


This paper is concerned with transforming depth p-nested for loop algorithms into q-dimensional systolic VLSI arrays where [formula omitted]. Previously there existed complete characterizations of correct transformations only for the cases when q = p – 1 or q = 1. We fill in this gap by giving formal necessary and sufficient conditions for correct transformation of a p-nested loop algorithm into a q-dimensional systolic array for any q, [formula omitted]. We also provide practical methods to derive optimal or suboptimal systolic array implementations. We apply the techniques developed by us to the automatic design of special purpose and programmable systolic arrays. Our results also contribute towards automatic compilation onto more general purpose programmable arrays. Synthesis of linear and planar systolic array implementations for a three-dimensional cube-graph algorithm and a reindexed Warshall-Floyd path-finding algorithm is used to illustrate our method.

Original languageEnglish (US)
Pages (from-to)64-76
Number of pages13
JournalIEEE Transactions on Parallel and Distributed Systems
Issue number1
StatePublished - Jan 1990


  • Algorithm transformations
  • automatic compilation
  • data dependence
  • matrix multiplication
  • nested loop algorithms
  • parallel processing
  • path-finding problems
  • systolic arrays

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Computational Theory and Mathematics


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