Memristor based programmable threshold logic array

Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose

doi:10.1109/NANOARCH.2010.5510933

Memristor based programmable threshold logic array

Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.

Original language	English (US)
Title of host publication	Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Pages	5-10
Number of pages	6
DOIs	https://doi.org/10.1109/NANOARCH.2010.5510933
State	Published - 2010
Event	2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 - Anaheim, CA, United States Duration: Jun 17 2010 → Jun 18 2010

Publication series

Name	Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Other

Other	2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Country/Territory	United States
City	Anaheim, CA
Period	6/17/10 → 6/18/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/NANOARCH.2010.5510933

Cite this

Rajendran, J., Manem, H., Karri, R., & Rose, G. S. (2010). Memristor based programmable threshold logic array. In Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 (pp. 5-10). Article 5510933 (Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010). https://doi.org/10.1109/NANOARCH.2010.5510933

Memristor based programmable threshold logic array. / Rajendran, Jeyavijayan; Manem, Harika; Karri, Ramesh et al.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010. 2010. p. 5-10 5510933 (Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rajendran, J, Manem, H, Karri, R & Rose, GS 2010, Memristor based programmable threshold logic array. in Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010., 5510933, Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, pp. 5-10, 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, United States, 6/17/10. https://doi.org/10.1109/NANOARCH.2010.5510933

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Memristor based programmable threshold logic array

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