TY - GEN
T1 - Methods and infrastructure in the era of accelerator-centric architectures
AU - Reagen, Brandon
AU - Shao, Yakun Sophia
AU - Xi, Sam Likun
AU - Wei, Gu Yeon
AU - Brooks, David
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/27
Y1 - 2017/9/27
N2 - Computer architecture today is anything but business as usual, and what is bad for business is often great for science. As Moore's Law continues to unwaveringly march forward, despite the ceasing of Dennard scaling, continued performance gains with each processor generation has become a significant challenge, and requires creative solutions. Namely, the way to continue to scale performance in light of power issues is through hardware specialization. Hardware accelerators promise not only orders of magnitude in performance improvements over general purpose processors, but sport similar energy efficiency gains. However, accelerators are equal parts problem solver as they are creator. The major problem is designing and integrating accelerators into a complex environment within the stringent SoC design cycles. Given that each accelerator has a rich design space and convoluted implications and interactions with the memory system, better mechanisms for studying this new-breed of SoC are needed. To usher in the new era of computer architecture, we have built Aladdin: a high-level accelerator simulator enabling rapid accelerator design. Aladdin was recently extended to operate in conjunction with gem5 to study memory system interactions. In this paper we will recount the operation and utilities of Aladdin and gem5-Aladdin, concluding with a case study of how Aladdin can be used to optimize DNN accelerators.
AB - Computer architecture today is anything but business as usual, and what is bad for business is often great for science. As Moore's Law continues to unwaveringly march forward, despite the ceasing of Dennard scaling, continued performance gains with each processor generation has become a significant challenge, and requires creative solutions. Namely, the way to continue to scale performance in light of power issues is through hardware specialization. Hardware accelerators promise not only orders of magnitude in performance improvements over general purpose processors, but sport similar energy efficiency gains. However, accelerators are equal parts problem solver as they are creator. The major problem is designing and integrating accelerators into a complex environment within the stringent SoC design cycles. Given that each accelerator has a rich design space and convoluted implications and interactions with the memory system, better mechanisms for studying this new-breed of SoC are needed. To usher in the new era of computer architecture, we have built Aladdin: a high-level accelerator simulator enabling rapid accelerator design. Aladdin was recently extended to operate in conjunction with gem5 to study memory system interactions. In this paper we will recount the operation and utilities of Aladdin and gem5-Aladdin, concluding with a case study of how Aladdin can be used to optimize DNN accelerators.
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U2 - 10.1109/MWSCAS.2017.8053070
DO - 10.1109/MWSCAS.2017.8053070
M3 - Conference contribution
AN - SCOPUS:85034080208
T3 - Midwest Symposium on Circuits and Systems
SP - 902
EP - 905
BT - 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
Y2 - 6 August 2017 through 9 August 2017
ER -