Negative Bias Temperature Instability (NBTI) is a prominent physical failure mechanism which severely degrades the performance of PMOS transistors whenever the voltage at the gate is negatively biased. It leads to catastrophic timing violations in critical circuits and a severe shortening of the overall operational lifetime of the entire system. To alleviate such damaging effects due to NBTI, we present PRITEXT, a novel technique which generates a minimal set of deterministic exercise vectors based on test generation techniques which inherently near-optimizes the bit patterns across each of the generated vectors; the end target being to exercise the critical paths of a device when dormant so as to achieve near-ideal NBTI stress reduction. We explore the design-space of our generated vectors and apply them to our test processor platform under differing sequences, where our evaluation under realistic benchmarks shows that PRITEXT leads to an average 4.99× and a maximum of 13.91× lifetime improvement using 9 generated vectors. In an attempt to reduce hardware overheads even further, we next propose a heuristic to further reduce the number of exercise vectors with minimum loss in lifetime improvement.