Mitigating the impact of process variation on the performance of 3-D integrated circuits

Keyphrases

• Multiple Clock Domains 100%
• 3D Design 50%
• Domain Design 50%
• Synchronous Clock 33%
• Integration Strategies 33%
• Percentage Yield 16%
• Scalable Technology 16%
• Die Stacking 16%
• Optimization Strategy 16%
• Variability-Aware 16%
• Promising Solutions 16%
• Design Meetings 16%
• Interconnect Delay 16%
• Stacked Architecture 16%
• Process Parameter Variation 16%

Engineering

• Design Domain 100%
• Process Parameter Variation 33%
• Optimization Strategy 33%
• Performance Constraint 33%
• Design Style 33%
• Design Meeting 33%

Computer Science

• Process Parameter Variation 50%
• Interconnect Delay 50%
• Design Framework 50%
• Optimization Strategy 50%