Mitigation of half-cycle saturation of adjacent transformers during hvdc monopolar operation-part II: Detecting zero-sequence fault currents

Ming Yang, Digvijay Deswal, Francisco De Leon

Research output: Contribution to journalArticle

Abstract

This two-part paper presents a method to mitigate half-cycle saturation of transformers caused by monopolar operation of neighboring HVDC transmission lines while keeping the ability to detect the zero-sequence fault currents (ZSFC) when ground faults occur. Part I of this paper has presented the mitigation principles and device design of the proposed neutral current blocking switch. In Part II, the performance of the proposed method to permit the circulation of zero-sequence current is investigated. An operation strategy is proposed that simultaneously allows the mitigation of half-cycle saturation and the detection of ZSFC. Simulations on a widely-used 500 kV system show that the proposed mitigation technique, using a sub-synchronous switching frequency (no higher than 30 Hz), can effectively mitigate the half-cycle saturation while allowing the circulation of ZSFC. The novel mitigation method exploits the characteristic differences between half-cycle saturation (dc) and asymmetric faults (ac). The method provides an implementable solution to the dc-bias phenomenon because it delivers concurrently dc-bias mitigation, minimal impact on ground fault detection, and no switching stresses on the power electronic switches. The proposed technique can also be applied to the mitigation of geomagnetically induced currents.

Original languageEnglish (US)
Article number8674531
Pages (from-to)16-24
Number of pages9
JournalIEEE Transactions on Power Delivery
Volume35
Issue number1
DOIs
StatePublished - Feb 2020

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Keywords

  • GIC
  • HVDC
  • half-cycle saturation
  • neutral switching
  • transformers
  • zero-sequence fault current

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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