TY - GEN
T1 - MoS2 FET fabrication and modeling for large-scale flexible electronics
AU - Yu, Lili
AU - El-Damak, Dina
AU - Ha, Sungjae
AU - Rakheja, Shaloo
AU - Ling, Xi
AU - Kong, Jing
AU - Antoniadis, Dimitri
AU - Chandrakasan, Anantha
AU - Palacios, Tomas
PY - 2015/8/25
Y1 - 2015/8/25
N2 - We present a state-of-the-art fabrication technology and physics-based model for molybdenum disulfide (MoS2) field effect transistors (FETs) to realize large-scale circuits. Uniform and large area chemical vapor deposition (CVD) growth of monolayer MoS2 was achieved by using perylene-3,4,9, 10-tetracarboxylic acid tetrapotassium salt (PTAS) seeding. Then, a gate first process results in enhancement mode FETs and also reduces performance variation and enables better process control. In addition, a Verilog-A compact model precisely predicts the performance of the fabricated MoS2 FETs and eases the large-scale integrated design. By using this technology, a switched capacitor DC-DC converter is implemented, and the measurement of the converter shows good agreement with the simulations.
AB - We present a state-of-the-art fabrication technology and physics-based model for molybdenum disulfide (MoS2) field effect transistors (FETs) to realize large-scale circuits. Uniform and large area chemical vapor deposition (CVD) growth of monolayer MoS2 was achieved by using perylene-3,4,9, 10-tetracarboxylic acid tetrapotassium salt (PTAS) seeding. Then, a gate first process results in enhancement mode FETs and also reduces performance variation and enables better process control. In addition, a Verilog-A compact model precisely predicts the performance of the fabricated MoS2 FETs and eases the large-scale integrated design. By using this technology, a switched capacitor DC-DC converter is implemented, and the measurement of the converter shows good agreement with the simulations.
KW - 2D materials
KW - MoS
KW - flexible IC
KW - large scale
UR - http://www.scopus.com/inward/record.url?scp=84951014271&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84951014271&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2015.7223655
DO - 10.1109/VLSIT.2015.7223655
M3 - Conference contribution
AN - SCOPUS:84951014271
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - T144-T145
BT - 2015 Symposium on VLSI Technology, VLSI Technology 2015 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Symposium on VLSI Technology, VLSI Technology 2015
Y2 - 16 June 2015 through 18 June 2015
ER -