Scan architectures with compression support have remedied the test time and data volume problems of today's sizable designs. On-chip compression of responses enables the transmission of a reduced volume signature information to the ATE, delivering test data volume savings, while it engenders the challenge of retaining test quality. In particular, unknown bits (x's) in responses corrupt other response bits upon being compacted altogether, masking their observation, and hence preventing the manifestation of the fault effects they possess. In this work, we propose the design and utilisation of a response compactor that can adapt to the varying density of x's in responses. In the proposed design, fan-out of scan chains to XOR trees within the compactor can be adjusted per pattern/slice so as to minimise the corruption impact of x's. A theoretical framework is developed to guide the cost-effective synthesis of multi-modal compactor that can deliver x-mitigation capabilities in every mode it operates. Adaptiveness of the proposed response compactor enhances the observability of scan cells cost-effectively, where observability enhancements can be tailored in a fault model-dependent or -independent manner, in either way improving test quality and/or test costs.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering