Multicast FullHD H.264 Intra Video Encoder Architecture

Muhammad Usman Karim Khan; Muhammad Shafique; Lars Bauer; Jorg Henkel

doi:10.1109/TCAD.2015.2446933

Multicast FullHD H.264 Intra Video Encoder Architecture

Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jorg Henkel

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

High throughput demands have resulted in enormous increase in complexity of multicast video applications, which require multiple video encoders to simultaneously compress individual views. In this paper, we present an approach to encode independent videos using H.264 intra encoder on a single hardware platform, where the hardware resources are shared by independent encoders in a time-multiplexed manner. In addition to lowering the latency introduced by multicasting, we address the strong sequential data dependencies within the encoder. At 25 frames/s, 150 MHz prototype of the proposed encoder and multiple video capture/display on a mid-range field programmable gate array is also presented.

Original language	English (US)
Article number	7128360
Pages (from-to)	2049-2053
Number of pages	5
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	34
Issue number	12
DOIs	https://doi.org/10.1109/TCAD.2015.2446933
State	Published - Dec 2015

Keywords

FPGA implementation
FullHD video encoder
H.264 encoder
hardware sharing
Multicast

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2015.2446933

Cite this

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Multicast FullHD H.264 Intra Video Encoder Architecture

Abstract

Keywords

ASJC Scopus subject areas

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