Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance

Wenjing Rao, Alex Orailoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Emerging nanoelectronics are expected to have very high manufacture-time defect rates and operation-time fault rates. Traditional N-modular redundancy (NMR) exploits the large device densities offered by these nanoelectronics to tolerate these high fault rates by allocating redundant resources according to the worst case fault rates. However, this approach is inflexible when the fault rates are time varying. In this paper, we propose a dynamically adaptive NMR approach by developing: (i) a genre of nanofabric topologies that supports sharing of redundancies in the NMR approach so as to adapt to the time varying fault rates and (ii) reconfiguration algorithms for these topologies to deal with fault tolerance loss caused by manufacturing defects and operation-time online faults, respectively. Simulation results verify that the ability to construct reliable systems, possibly the paramount consideration in constructing working applications in nanoelectronics, is significantly improved with the proposed flexible NMR architecture and the reconfiguration algorithms.

Original languageEnglish (US)
Title of host publicationProceedings - 24th IEEE VLSI Test Symposium
Pages214-219
Number of pages6
DOIs
StatePublished - 2006
Event24th IEEE VLSI Test Symposium - Berkeley, CA, United States
Duration: Apr 30 2006May 4 2006

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2006

Other

Other24th IEEE VLSI Test Symposium
CountryUnited States
CityBerkeley, CA
Period4/30/065/4/06

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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  • Cite this

    Rao, W., Orailoglu, A., & Karri, R. (2006). Nanofabric topologies and reconfiguration algorithms to support dynamically adaptive fault tolerance. In Proceedings - 24th IEEE VLSI Test Symposium (pp. 214-219). [1617592] (Proceedings of the IEEE VLSI Test Symposium; Vol. 2006). https://doi.org/10.1109/VTS.2006.50