NREPO: Normal basis recomputing with permuted operands

Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hardware implementations of cryptographic algorithms are vulnerable to natural and malicious faults. Concurrent Error Detection (CED) can be used to detect these faults. We present NREPO, a CED which does not require redundant computational resources in the design. Therefore, one can integrate it when computational resources are scarce or when the redundant resources are difficult to harness for CED. We integrate NREPO in a low-cost Advanced Encryption Standard (AES) implementation with 8-bit datapath. We show that NREPO has 25 and 50 times lower fault miss rate than robust code and parity, respectively. The area, throughput, and power are compared with other CEDs on 45nm ASIC. The hardware overhead of NREPO is 34.9%. The throughput and power are 271.6Mbps and 1579.3μW, respectively. One can also implement NREPO in other cryptographic algorithms.

Original languageEnglish (US)
Title of host publicationProceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014
PublisherIEEE Computer Society
Pages118-123
Number of pages6
ISBN (Print)9781479941148
DOIs
StatePublished - 2014
Event2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014 - Arlington, VA, United States
Duration: May 6 2014May 7 2014

Publication series

NameProceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014

Other

Other2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014
CountryUnited States
CityArlington, VA
Period5/6/145/7/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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