TY - GEN
T1 - NREPO
T2 - 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014
AU - Guo, Xiaofei
AU - Mukhopadhyay, Debdeep
AU - Jin, Chenglu
AU - Karri, Ramesh
PY - 2014
Y1 - 2014
N2 - Hardware implementations of cryptographic algorithms are vulnerable to natural and malicious faults. Concurrent Error Detection (CED) can be used to detect these faults. We present NREPO, a CED which does not require redundant computational resources in the design. Therefore, one can integrate it when computational resources are scarce or when the redundant resources are difficult to harness for CED. We integrate NREPO in a low-cost Advanced Encryption Standard (AES) implementation with 8-bit datapath. We show that NREPO has 25 and 50 times lower fault miss rate than robust code and parity, respectively. The area, throughput, and power are compared with other CEDs on 45nm ASIC. The hardware overhead of NREPO is 34.9%. The throughput and power are 271.6Mbps and 1579.3μW, respectively. One can also implement NREPO in other cryptographic algorithms.
AB - Hardware implementations of cryptographic algorithms are vulnerable to natural and malicious faults. Concurrent Error Detection (CED) can be used to detect these faults. We present NREPO, a CED which does not require redundant computational resources in the design. Therefore, one can integrate it when computational resources are scarce or when the redundant resources are difficult to harness for CED. We integrate NREPO in a low-cost Advanced Encryption Standard (AES) implementation with 8-bit datapath. We show that NREPO has 25 and 50 times lower fault miss rate than robust code and parity, respectively. The area, throughput, and power are compared with other CEDs on 45nm ASIC. The hardware overhead of NREPO is 34.9%. The throughput and power are 271.6Mbps and 1579.3μW, respectively. One can also implement NREPO in other cryptographic algorithms.
UR - http://www.scopus.com/inward/record.url?scp=84905976364&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84905976364&partnerID=8YFLogxK
U2 - 10.1109/HST.2014.6855581
DO - 10.1109/HST.2014.6855581
M3 - Conference contribution
AN - SCOPUS:84905976364
SN - 9781479941148
T3 - Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014
SP - 118
EP - 123
BT - Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2014
PB - IEEE Computer Society
Y2 - 6 May 2014 through 7 May 2014
ER -